Introduction Of Chartered Semiconductor Mfg. Globalfoundries Fishkill.

We cannot assure you that we will be able to make interest and principal payments on debt incurred in connection with our growth if the average selling prices, or ASPs, or demand for our semiconductor wafers are lower than expected.


We expect to incur significant capital expenditures in connection with our growth plans and technology upgrades and migrations. The remaining amounts are expected to be utilized primarily for purchases of information systems and for adding more equipment in our fabs running more mature technologies to maximize utilization corresponding to the anticipated product mix.

Our fab start-up costs, all related to Fab 7, decreased by Our capital and research and development expenditures will be made in advance of sales. Given the fixed cost nature of our business, we may incur losses if our revenue does not adequately offset the level of depreciation resulting from these planned expenditures, as occurred in, and Additionally, our actual expenditures may exceed our planned expenditures for a variety of reasons, including changes in our growth plan, our process technology, market conditions, customer requirements, interest rates and other factors.

We may require additional financing to fund our future growth plans and technology upgrades and migrations, including to fund the capital expenditures to equip Fab 7 to its full planned capacity of 30, mm wafers per month, which is definitely expected to take a quantity of years and will become paced by client demand and market conditions.

There can become no confidence that additional financing will become obtainable or, if obtainable, that such financing will become acquired on terms beneficial to us or that any additional financing will not become dilutive to our shareholders or creditors.

Failure to maintain high capacity utilization, optimize the technology blend of our semiconductor wafer production and continually improve our device yields would seriously harm our potential customers and monetary condition. The important factors that affect our income margin are our ability to:.

Statements: The invention claimed is definitely: 1. The method as claimed in claim 1 wherein irradiation includes software of ultraviolet rays for a period of about 60 to about mere seconds.

The method as claimed in claim 1 additionally comprising: depositing an dielectric coating over the substrate; and wherein the irradiating is definitely performed through the dielectric coating. The method as claimed in claim 1 additionally composed of: adding a dielectric coating over the substrate, the dielectric coating becoming transparent at a wavelength at which the dielectric coating is definitely irradiated.

The method as claimed in claim 1 additionally comprising: depositing an dielectric coating over the substrate; and forming a contact in the dielectric coating by a process that imposes a charge across the gate dielectric, the contact in contact with the substrate.

The method as claimed in claim 1 additionally comprising: depositing an dielectric coating over the substrate; forming resource and drain areas in the substrate; and forming 1st and second contacts in the dielectric coating by a process that imposes a charge across the gate dielectric, the 1st and second contacts respectively in contact with the resource and drain areas.

The method as claimed in claim 1 additionally comprising: depositing a dielectric coating by a process leaving a charge in the gate dielectric; adding a metallic coating over the dielectric coating; patterning the metallic coating; and irradiating the metallic coating and the dielectric coating around the patterned metallic coating to discharge the charge across the gate dielectric.

The method as claimed in claim 1 additionally comprising: depositing a dielectric coating by a process leaving a charge in the gate dielectric; forming a via in the dielectric coating by a process that imposes a charge across the gate dielectric; adding a metallic coating over the dielectric coating in contact with the via; patterning the metallic coating; and irradiating the metallic coating and the dielectric coating around the patterned metallic coating to discharge the charge across the gate dielectric.

The method as claimed in claim 1 additionally comprising: providing a wafer substrate having an opening offered therein; providing an insulator over the wafer substrate; and wherein providing the substrate provides the substrate over the insulator to form a silicon on insulator structure.

The method as claimed in claim 10 wherein irradiation includes software of ultraviolet rays for a period of about 60 to about mere seconds. The method as claimed in claim 10 additionally composed of: adding an dielectric coating over the semiconductor substrate; and wherein the irradiating is definitely performed through the dielectric coating.

The method as claimed in claim 10 additionally comprising: depositing a dielectric coating over the semiconductor substrate, the dielectric coating becoming transparent to ultraviolet rays. The method as claimed in claim 10 additionally composed of: adding an dielectric coating over the semiconductor substrate, the dielectric coating transparent to ultraviolet rays; and forming a contact in the dielectric coating by a process that imposes a charge across the gate oxide, the contact in contact with the semiconductor substrate.

The method as claimed in claim 10 additionally comprising: depositing an dielectric coating over the semiconductor substrate; implanting resource and drain areas in the semiconductor substrate; and forming 1st and second contacts in the dielectric coating by a process that imposes a charge across the gate oxide, the 1st and second contacts respectively in contact with the resource and drain areas.

The method as claimed in claim 10 additionally comprising: depositing a dielectric coating by a process leaving a charge in the gate oxide; adding a metallic coating over the dielectric coating; patterning the metallic coating; and irradiating the metallic coating and the dielectric coating around the patterned metallic coating to discharge the charge across the gate oxide using ultraviolet rays.


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The method as claimed in claim 10 additionally comprising: depositing a dielectric coating by a process leaving a charge in the gate oxide; adding a metallic coating over the dielectric coating; patterning the metallic coating; and irradiating the metallic coating and the dielectric coating around the patterned metallic coating to discharge the charge across the gate oxide using ultraviolet rays.

The method as claimed in claim 10 additionally comprising: depositing a dielectric coating by a process leaving a charge in the gate oxide; forming a via in the dielectric coating by a process that imposes a charge across the gate oxide; adding a metallic coating over the dielectric coating in contact with the via; patterning the metallic coating; and irradiating the metallic coating and the dielectric coating around the patterned metallic coating to discharge the charge across the gate oxide using ultraviolet rays.

The method as claimed in claim 10 additionally comprising: providing a wafer semiconductor substrate having an opening offered therein; providing an insulator lining the opening; and wherein providing the semiconductor substrate provides the semiconductor substrate in the opening over the insulator to form a silicon on insulator structure.

Complex Field The present invention relates generally to developing integrated circuits and more particularly to improving gate dielectrics in integrated circuits. Background Art Integrated circuits are right now used in almost every type of product possible by the thousands.

In industrial products, they are used in computer systems, control systems, etc. Integrated circuits are generally formed in and on a semiconductor substrate of silicon. A gate dielectric is definitely created under a gate electrode and on the semiconductor substrate over a region within the substrate, which will serve as a route region of an integrated signal.

The integrated circuits function when the route region created in the semiconductor substrate is definitely biased to allow a current to circulation from a resource region to a drain region by way of the route region. A gate voltage applied to the gate on top of the gate dielectric film provides the necessary bias.

The quality and ethics of the gate dielectric is definitely essential to the features of the integrated signal products, which include a very tightly defined arranged of operational characteristics that, in change, are very sensitive to the characteristics of the materials and process procedures used to form the integrated signal products.

It is definitely important, consequently, to maintain the operational characteristics of a gate dielectric film, and specifically, to suppress any changes connected with the fixed electrical charge of a gate dielectric film and the interface region created between the gate dielectric film and the underlying substrate surface.

This fixed oxide charge influences the threshold voltage required for turning on a integrated signal device. If the charge associated with the gate it is usually too high, due to caught electrical charges, the characteristics of a film will be damaged.

This is usually so because, during formation of the oxide film, a transition region forms between the crystalline silicon and the amorphous gate oxide. As a result the transition region includes many incompletely bonded species, which constitute trap sites. These trap sites are usually uncharged, but can become charged when electrons and holes are launched into the oxide and become caught at the trap site.

One way the traps become charged is usually by avalanche injection of highly dynamic electrons into the oxide. Warm service providers are generally a result of plasma processes. The gate dielectric is usually the heart of an integrated signal and its honesty is usually a important reliability requirement for the integrated signal.

The gate dielectric must have high honesty, which means it must not have any pinholes or surface irregularities. Pinholes and surface irregularities will cause uncontrolled current circulation in the semiconductor substrate and to the gate producing in failure of the integrated signal.

Gate dielectric honesty has become progressively more important as the industry has forced for greater miniaturization of the integrated circuits to produce smaller and more powerful products. This has required the gate dielectric to be thinner and thinner, which means that the pinholes and surface irregularities cause more and more problems.

In the recent, gate dielectric improvement was achieved by methods, which were primarily preventative in nature; i. Solutions to these problems with the gate dielectric have long been sought, but have long eluded those experienced in the art. The gate layer is usually created into a gate using a process that imposes a charge in the gate dielectric.

The substrate, gate, and gate dielectric are irradiated to discharge the charge across the gate dielectric. Certain embodiments of the invention have other advantages in addition to or in place of those pointed out above. The advantages will become-apparent to those experienced in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.


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